
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity packetgen is
    Port ( clk     : in  STD_LOGIC;
           reset   : in  STD_LOGIC;
		  	  i_ready : in STD_LOGIC;
			  din     : in STD_LOGIC_VECTOR (127 downto 0);
			  dout    : out STD_LOGIC_VECTOR (127 downto 0);
			  o_ready : out  STD_LOGIC);
end packetgen;



architecture packetgen_arch of packetgen is

type statetype is ( S1, S2, S3, S4 );
signal state, next_state : statetype := S1;


begin

process (clk, reset) is

end process

end packetgen_arch;

